Posts Tagged ‘opteron vs nehalem’

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Operton vs. Nehalem-EP at AnandTech

May 22, 2009

AnandTech’s Johan DeGelas has an interesting article on what he calls “real world virtualization” using a benchmark process his team calls “vApus Mk I” and runs it on ESX 3.5 Update 4. Essentially, it is a suite of Web 2.0 flavored apps running entirely on Windows in a mixed 32/64 structure. We’re cautiously encouraged by this effort as it opens the field of potential reviewers wide open.

Additionally, he finally comes to the same conclusion we’ve presented (in an economic impact context) about Shanghai’s virtualization value proposition. While his results are consistent with what we have been describing – that Shanghai has a good price-performance position against Nehalem-EP – there are some elements about his process that need further refinement.

Our biggest issue comes with his handling of 32-bit virtual machines (VM) and disclosure of using AMD’s Rapid Virtualization Indexing (RVI) with 32-bit VMs. In the DeGalas post, he points out some well known “table thrashing” consequences of TLB misses:

“However, the web portal (MCS eFMS) will give the hypervisor a lot of work if Hardware Assisted Paging (RVI, NPT, EPT) is not available. If EPT or RVI is available, the TLBs (Translation Lookaside Buffer) of the CPUs will be stressed quite a bit, and TLB misses will be costly.”

However, the MCS eFMS web portal (2 VMs) is running in a 32-bit OS. What makes this problematic is VMware’s default handling of page tables in 32-bit VM’s is “shadow page table” using VMware’s binary translation engine (BT). In otherwords, RVI is not enabled by default for ESX 3.5.x:

“By default, ESX automatically runs 32bit VMs (Mail, File, and Standby) with BT, and runs 64bit VMS (Database, Web, and Java) with AMD-V + RVI.”

–    VROOM! Blog, 3/2009

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